MPC7450 microprocessors feature a high-frequency superscalar PowerPC core, capable of issuing four instructions per clock cycle (three instructions + branch) into eleven independent execution units:

• Four integer units (3 simple + 1 complex)
• Double-precision floating-point unit
• Four AltiVec units (simple, complex, floating, and permute)
• Load/store unit
• Branch processing unit

Cache and MMU Support

The MPC7450 microprocessor has separate 32KB, physically addressed instruction and data caches. Both L1 caches feature cache way locking and are eight-way set associative. For greater speed, the L2 cache has been integrated on-chip with a 256-bit interface to L1 which operates at processor frequency. This L2 is 256KB eight-way set associative. L2 cache access is fully pipelined. The MPC7450 also supports an L3 cache interface with on-chip tags to support up to 2MB of off-chip cache. The L3 data bus is 64-bits wide, provides multiple SRAM options, and affords critical quad-word forwarding to reduce latency. The off-chip L3 storage can also be configured as a local addressable memory. Finally, in addition to supporting hardware table searching on a TLB miss, the MPC7450 can be configured for software table searching. In this case, TLB entries are loaded by the system software.

The MPC7450 microprocessor contains separate memory management units for instructions and data, supporting 4 Petabytes (252) of virtual memory and up to 64 Gigabytes (236) of physical memory. The MPC7450 also has four instruction block address translation and four data block address translation registers.

MPX Bus Interface

MPC7450 microprocessors support the MPX bus protocol with a 64-bit data bus and a 32- or 36-bit address bus. Support is included for burst, split, pipelined and out-of-order transactions, in addition to data streaming, and data intervention (in SMP systems). The interface provides snooping for data cache coherency. The MPC7450 implements the cache coherency protocol for multiprocessing support in hardware, allowing access to system memory for additional caching bus masters, such as DMA devices.

Power Management

MPC7450 microprocessors feature a low-power 1.8-volt design with three power-saving user-programmable modes -- nap, doze (with bus snoop) and sleep -- which progressively reduce the power drawn by the processor. The MPC7450 also provides a thermal assist unit and instruction cache throttling for software-controllable thermal management.

AltiVec™ Technology

The AltiVec technology expands the capabilities of Motorola's fourth generation PowerPC microprocessors by providing leading-edge, general purpose processing performance while concurrently addressing high-bandwidth data processing and algorithmic-intensive computations in a single-chip solution. AltiVec technology:

• Meets the computational demands of networking infrastructure such as echo cancellation equipment, and base station processing.
• Enables faster, more secure encryption methods optimized for the SIMD processing model.
• Provides compelling performance for multimedia-oriented desktop computers, desktop publishing, and digital video processing.
• Enables real-time processing of the most demanding data streams (MPEG-2 encode, continuous speech recognition, real-time high-resolution 3D memory for 3D graphics.)